1. Field of the Invention
The present invention relates to a monitoring circuit and method for provision within a device such as an integrated circuit in order to monitor a performance characteristic of components of that device, in situations where the performance characteristic is dependent on one or more physical properties of the components.
2. Description of the Prior Art
When an integrated circuit, such as a memory circuit, is designed, various performance parameters of that integrated circuit typically need to be selected by the designer. In the case of memory circuits, the designers use various margining methodologies during the design stage to set parameters such as, for example, the timing of the sense amplifiers. As process technologies scale to smaller geometries, the variations between different instances of an integrated circuit become greater such that in order to ensure correct operation of worst-case bit cells and the like across the full range of process-voltage-temperature (PVT) parameters, these design margins are becoming increasingly large and impose a performance constraining limitation upon the integrated circuit, even if that particular integrated circuit would in fact be capable of much higher performance. These large margins to deal with increasing process variation result in a loss of frequency performance, increased power consumption and/or other performance reductions.
Process variation is an example of a performance characteristic that is dependent on one or more physical properties of the components within a device. For example, variations in doping concentrations may give rise to variations in performance. As mentioned above, these process variations increase as process technology scales to smaller geometries. It is known to categorise the process variations using so-called process corners. One naming convention for process corners is to use two-letter designators, where the first letter refers to the N-channel MOSFET (NMOS) corner, and the second letter refers to the P-channel MOSFET (PMOS) corner. In this naming convention, three corners exist, namely typical (T), fast (F) and slow (S) corners. Fast and slow corners exhibit carrier mobilities that are higher and lower than normal, respectively. For example, a corner designated as FS denotes fast NFETS and slow PFETS.
If the process corner applicable to a particular instance of a device could be detected in situ, it would allow a reduction in the margins that were required. However, the known techniques for seeking to detect process variation suffer from a number of disadvantages, as will be discussed below.
The article “On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit” by A Ghosh et al, 21st International Conference on VLSI Design, IEEE 2008, uses a slew rate monitor to detect process. The slew rate monitor circuit uses two comparators with different reference voltages, such that the comparators then switch at different times dependent on the slew. The slew is then used as a metric along with delay to determine the mismatch between the drive strength of NMOS and PMOS devices. However, this circuit is very sensitive to comparator offset, and also its accuracy is dependent on various analog components. Due to the dependency of the circuit on analog components, the overall accuracy of the circuit may be limited. The analog nature of the circuit is also likely to cause issues across various process geometries, since generally analog circuits do not behave the same way as those process geometries change. Such an approach is hence likely to be too complex, inaccurate, and lacking in scalability across different technologies.
The article “A Process Variation Detection Method” by V Melikyan et al, IEEE 2010, also uses an analog circuit to detect process variation and accordingly suffers from similar disadvantages to those outlined above.
The article “Techniques for On-Chip Process Voltage and Temperature Detection Compensation” by Q Khan et al, describes a number of techniques for on-chip PVT detection and compensation. Two circuits are discussed, the first providing delay locked loop (DLL) based PVT compensation, and the second providing ring oscillator based PVT compensation. Whilst the techniques described in this article use a more digital approach than that in the preceding two articles, the circuits used are relatively complex. Whilst the technique described allows for accurate detection of the process, the overhead is likely to make it an impractical solution for many situations, for example in memory devices where overhead is a key concern.
Accordingly, it would be desirable to provide a simple and accurate mechanism for detecting variation in a performance characteristic such as process variation, which is more readily scalable across process technologies.